Wiring substrates of various shapes and structures are used to mount components such as semiconductor chips and the like. The thinning and miniaturization of semiconductor chips has resulted in demands for a thinner and smaller wiring substrate used for the mounting of semiconductor chips. In the manufacturing of such a wiring substrate, filled vias, wirings, and the like are formed. Japanese Laid-Open Patent Publication No. 2009-88282 describes a method for manufacturing a printed wiring board using a laser via processing. One example of a method for forming the filled via and the wiring will now be described below.
As illustrated in FIG. 7A, a core material 90 including two opposite surfaces to which copper foils 91, 92 are adhered is first prepared. Then, in the step illustrated in FIG. 7B, a laser processing method is used to form an opening 92X in the copper foil 92 and to form a through hole 90X, which communicates with the opening 92X and extends through the core material 90 to expose the copper foil 91. When forming the opening 92X and the through hole 90X with the laser processing method, the laser processing proceeds faster in the core material 90 (resin layer) than in the copper foil 92. Thus, the through hole 90X of the core material 90 is formed extending into the lower side of the copper foil 92 from the opening 92X. In other words, an overhang structure is formed at the upper part of the through hole 90X. The overhang structure is a structure in which a projection 92A of the copper foil 92 projects to the inner side of the through hole 90X. Thereafter, the resin smear (resin residual) in the through hole 90X is removed through desmear processing.
Next, in the step illustrated in FIG. 7C, the projection 92A of the copper foil 92 is removed by etching and the like. In the step illustrated in FIG. 7D, a seed layer 93 is formed to cover the inner surfaces of the through hole 90X and the opening 92X and the exposed surfaces of the core material 91 and the copper foils 91, 92. In the step illustrated in FIG. 7E, an electrolytic plating method is performed using the seed layer 93 and the copper foil 91 as plating power supplying layers. This forms a filled via 94, which fills the through hole 90X and the opening 92X, a conductive layer 95, which covers the filled via 94 and the copper foil 92, and a conductive layer 96, which covers the entire lower surface of the copper foil 91. Further, in the step illustrated in FIG. 7E, the copper foil 92 and the conductive layer 95, as well as the copper foil 91 and the conductive layer 96 are patterned using a subtractive method and the like. This forms a wiring layer 97 on the upper surface of the core material 90 and forms a wiring layer 98 on the lower surface of the core material 90. As a result, the wiring layer 97 at the upper surface of the core material 90 is electrically connected to the wiring layer 98 at the lower surface of the core material 90 by the filled via 94.
In the manufacturing method described above, plating such as copper is deposited from the seed layer 93 formed on the inner surfaces of the through hole 90X and the opening 92X, so that the filled via 94 is filled in the through hole 90X. However, when an aspect ratio (depth/radius) of the through hole 90X is large, for example, when the through hole 90X is deep, the filling property of the plated film, that is, the filled via 94 degrades. Thus, a recess 99 may be easily formed at the surface of the filled via 94 (wiring layer 97) as illustrated in FIG. 7F.